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Honored Contributor
Honored ContributorUse PLL between the dedicated clock input pin and output pin.
I am using the cyclone II series, and my global clock(32M,input_clk) is inputed by a dedicated clock input pin(clk0). Now I need a clock which is 4MHz divided by input_clk, and output it to a ...
Altera_ForumHonored Contributor
Honored ContributorRight out of my head the slowest clock a cyclone II pll can generate is ~12MHz
plls in cyclone ii devices (http://www.altera.com/literature/hb/cyc2/cyc2_cii51007.pdf)
