Altera_Forum
Honored Contributor
Honored ContributorURGENT: Peripheral to Memory DMA Transaction
Hello, may I know how to transfer data from peripheral to memory using DMA? It is quite confusing from memory-to-memory transfer. please help! thanks!
Forum Discussion
111 Replies
Altera_ForumOK. i am trying now and will post the result.
- Altera_Forum
hi... i have done doing the block... i can get the result now and the result is correct... but the time it fetch the result is different... pls see the attachment..
p/s: as for now, i didnt use address for adder anymore. once chipselect is high, it will fetch data into the adder, calculate it and fetch the result to the output at the same time. - Altera_Forum
Why did you connect the avalon read signal to the incoming fifo?
The avalon reads data from the outgoing, does it? The read signal from the incoming fifo should come from the adder, as this one reads data from the fifo, or does it? The readrq for the incoming fifo and the write signal for the adder should come from chipselect&clk. I like the trick with the read/write enables for the fifo. Of course the data needs some clock cycles to move through the fifo... - Altera_Forum
Yeah, i did edit the signal... the result still the same... does it consider as correct for the result?
hahaha. i dont know how to connect the signal to interrupt, so i just use tristate buffer. in the attachment, the picture (block.jpg) is the overall block. now i have the block, how to connect that block with DMA? - Altera_Forum
You're using SOPC-Builder, do you?
A DMA is just 2 Avalon masters, one for reading and one for writing. You want to transmit data from where to where? - Altera_Forum
Yes, SOPC. I want to transfer from SDRAM to this block then from this block to SDRAM back.
Update: I tried to run it in Nios II IDE, but the result i got were wrong... correct result: 0, 2, 4, 6, 8....298 result obtained: 294, 296, 0, 2, 4...292 i am adding number 0 till 149... suppose 294 = 147+147 is it because of the delay in fetching the result previously? if yes, how to solve it? thanks! - Altera_Forum
How much data have you fed it?
How high is the fifo fill count (usedw)? Might it already have wrapped around somehow, and read old values from a previous run? Have you tried to feed it different values? - Altera_Forum
yes, the data was due to previous run. initial run (1st time), the initial result is 0,0,200, 0,2,4,6.... second run, the result was as in above. is it due to the block is running under same clock? 1st positive edge of the clk, 2nd read the data, 3rd data go into adder, 4th data go into fifo_out, 5th, data go out to be displayed as result.
- Altera_Forum
yes, exactly.
When you read from an empty fifo, the result is not really predictable. That's why one would check before, how many values are stored in it, and maybe erase old contents. Using an address decoder, you can trigger different actions (like, erase all fifos, set a halt condition on the adder, read the usedw value instead of a result,...). That's what creates the register representation in a periphereal. Have you had a look at the avalon master PIO example? That shows quite a lot of this concept. - Altera_Forum
I see. No, I dont have the example. Is it that I have to re-do?
