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Altera_Forum
Honored Contributor
15 years agoyes, exactly.
When you read from an empty fifo, the result is not really predictable. That's why one would check before, how many values are stored in it, and maybe erase old contents. Using an address decoder, you can trigger different actions (like, erase all fifos, set a halt condition on the adder, read the usedw value instead of a result,...). That's what creates the register representation in a periphereal. Have you had a look at the avalon master PIO example? That shows quite a lot of this concept.