Altera_Forum
Honored Contributor
Honored ContributorURGENT: Peripheral to Memory DMA Transaction
Hello, may I know how to transfer data from peripheral to memory using DMA? It is quite confusing from memory-to-memory transfer. please help! thanks!
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Altera_Forumwhy reset is high? i thought reset = 0 for the system to work.
- Altera_Forum
You use reset = 1 when the reset signal is active low (reset_n). If you have an active low reset and you hardcode it low then you'll get stuck in reset.
- Altera_Forum
Yes but my system reset is active high.
- Altera_Forum--- Quote Start --- You should read more about Avalon Interface Spec. --- Quote End --- Hi, thanks! Yeah but the spec is long. Maybe if possible, could you please tell me which section? Because I am running out of time. I need to get this done by this week. Thanks!
- Altera_Forum
if you have a Fifo, you should not connect chipselect and write/read signals to your adder. Rather you connect them to your incoming/outgoing fifo, as that is where you write/read the data.
Actually, the fifos should decouple the adder completely from the avalon interface. The write and chipselect lines to your adder should be fed by an internal logic, which is not too difficult: write could be just clock, while chipselect is (fifo_in_not_empty and fifo_out_not_full). So your adder works with the data as long as your fifos allow. - Altera_Forum
Hi. does it mean that for my adder, i dont have to put clock, reset and chipselect signals? Then for the write signal at adder, i connect it to clock. however for the address at adder, '0' means write the data in to be calculated and '1' means read the result to readdata to display the output. where should i connect it? thanks!
- Altera_Forum
besides, is it possible for FIFO to write and read at the same time?
- Altera_Forum
You certainly need a reset, to have a clear start condition.
You certainly need some clock, or nothing will work. As said above, the chipselect I would connect to fifo_in_not_empty <AND> fifo_out_not_full, so your adder stops when the fifos are empty/full. The write signal for your adder is the same as the read signal for incoming fifo (as the date read from it shall be written to the adder). Does you adder give a signal when it's done processing? That should go then to outgoing_fifo write signal. Use the address signals for the incoming fifo write and outgoing fifo read. You'll need to <AND> it with the avalon write signal, so you don't write data into the incoming fifo when accidentally reading from address 0. (Same goes for outgoing fifo.) - Altera_Forum--- Quote Start --- Does you adder give a signal when it's done processing? That should go then to outgoing_fifo write signal. --- Quote End --- No, once it adds the two number, i will wait for address = '1', then it will send the result out. --- Quote Start --- Use the address signals for the incoming fifo write and outgoing fifo read. You'll need to <AND> it with the avalon write signal, so you don't write data into the incoming fifo when accidentally reading from address 0. (Same goes for outgoing fifo.) --- Quote End --- this part is a bit confusing. the avalon write signal is the external signal? when address = 0, the data will be written into adder, when address = 1, the result will be sent out from adder. besides, can FIFO write and read at the same, which means, wrreq and rdreq both is high at the same time?
- Altera_Forum
yes. the M9K blocks are dual-interface ram blocks, that can be read and written at the same time.
the avalon has a write and a read signal. How else could you determine, whether to write to or read from the specified address? The address lines are there to select, which register (in your case fifo) to read from or write to. For the fifo design, theres no need for the adder to wait for anything. It could just output the write signal to the fifo, and all is good.
