URGENT: Peripheral to Memory DMA Transaction

You certainly need a reset, to have a clear start condition.

You certainly need some clock, or nothing will work.

As said above, the chipselect I would connect to fifo_in_not_empty <AND> fifo_out_not_full, so your adder stops when the fifos are empty/full.

The write signal for your adder is the same as the read signal for incoming fifo (as the date read from it shall be written to the adder). Does you adder give a signal when it's done processing? That should go then to outgoing_fifo write signal.

Use the address signals for the incoming fifo write and outgoing fifo read.

You'll need to <AND> it with the avalon write signal, so you don't write data into the incoming fifo when accidentally reading from address 0. (Same goes for outgoing fifo.)