URGENT: Peripheral to Memory DMA Transaction

if you have a Fifo, you should not connect chipselect and write/read signals to your adder. Rather you connect them to your incoming/outgoing fifo, as that is where you write/read the data.

Actually, the fifos should decouple the adder completely from the avalon interface.

The write and chipselect lines to your adder should be fed by an internal logic, which is not too difficult: write could be just clock, while chipselect is (fifo_in_not_empty and fifo_out_not_full). So your adder works with the data as long as your fifos allow.