URGENT: Peripheral to Memory DMA Transaction

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Does you adder give a signal when it's done processing? That should go then to outgoing_fifo write signal.

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No, once it adds the two number, i will wait for address = '1', then it will send the result out.

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Use the address signals for the incoming fifo write and outgoing fifo read.

You'll need to <AND> it with the avalon write signal, so you don't write data into the incoming fifo when accidentally reading from address 0. (Same goes for outgoing fifo.)

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this part is a bit confusing. the avalon write signal is the external signal? when address = 0, the data will be written into adder, when address = 1, the result will be sent out from adder.

besides, can FIFO write and read at the same, which means, wrreq and rdreq both is high at the same time?