URGENT: Peripheral to Memory DMA Transaction

Why did you connect the avalon read signal to the incoming fifo?

The avalon reads data from the outgoing, does it?

The read signal from the incoming fifo should come from the adder, as this one reads data from the fifo, or does it?

The readrq for the incoming fifo and the write signal for the adder should come from chipselect&clk.

I like the trick with the read/write enables for the fifo.

Of course the data needs some clock cycles to move through the fifo...