up/down counter

and when the counter reaches 0 it will display .F

What have you written so far and what problems are you encountering?

library ieee;

so depending on a signal you want it to either count up or down, what hardware do you expect?

Hello Malvin,

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- interface with the pins of the fpga (imported file .csv for pin planner)
entity ent_main is
   port(
    -- clock on DE board:
    clock2_50: in std_logic;
    
    -- reset button:
    reset_n : in std_logic;
    
    -- push buttons:
    key: in std_logic_vector(3 downto 0);
    
    -- hex 7 seg displays:
    hex0: out std_logic_vector(6 downto 0);
    hex1: out std_logic_vector(6 downto 0)
    );
     
end ent_main;
architecture arch_main of ent_main is
signal counter : integer range 0 to 255;
signal okey    : std_logic_vector(3 downto 0);
begin
  -- counter logic:
  process(clock2_50)
  begin  
    if (clock2_50'event and clock2_50='1') then
        if (reset_n='0') then   -- reset button pressed ?
            counter   <= 0;      -- reset counter
            okey      <= "0000"; -- helper value to rememer previous state of buttons
        else
            if (key(0)='0' and okey(0)='1') then -- this cycle button pressed and previous cycle not pressed
                counter<=counter+1; -- increment counter
            elsif (key(1)='0' and okey(1)='1') then -- this cycle button pressed and previous cycle not pressed
                counter<=counter-1; -- increment counter
            else
                counter<=counter; -- keep counter value
            end if;    
            okey <= key; -- remember previous value of counter
        end if;
    end if;
  end process;
    
  -- display hex value on 7-seg 
  -- display bits 0 to 3 on first part of 7seg
  led0: entity work.ent_led7seg(arch_led7seg)
        port map(data=>std_logic_vector(to_unsigned(counter,8))(3 downto 0),leds=>hex0);
  -- display bits 7 to 4 on first part of 7seg
  led1: entity work.ent_led7seg(arch_led7seg)
        port map(data=>std_logic_vector(to_unsigned(counter,8))(7 downto 4),leds=>hex1);
  
 end arch_main;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent_led7seg is
   port(data: in std_logic_vector(3 downto 0);
         leds : out std_logic_vector(6 downto 0)
       );
end ent_led7seg;
architecture arch_led7seg of ent_led7seg is
begin
    with data select
        leds<="1000000" when "0000",
              "1111001" when "0001",
              "0100100" when "0010",
              "0110000" when "0011",
              "0011001" when "0100",
              "0010010" when "0101",
              "0000010" when "0110",
              "1111000" when "0111",
              "0000000" when "1000",
              "0010000" when "1001",
              "0001000" when "1010",
              "0000011" when "1011",
              "1000110" when "1100",
              "0100001" when "1101",
              "0000110" when "1110",
              "0001110" when "1111",
              "0001000" when others;
  
end arch_led7seg;

Does this two codes work together?

Hello Malvin,

I just re-read your question and noticed you want to write an altera program. You should look into the differences between hardware (everything gets done at the same time) and software (everything gets done sequentially, disregarding multithreading).

Check out this online training. It will give you lots of the basic info you need to write an HDL. As mentioned you have to think in terms of hardware instead of software.