up/down counter

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity counter is

port ( clk : in std_logic;

reset_bar : in std_logic;

q : out std_logic_vector (2 downto 0));

end counter;

architecture flow of counter is

signal count_sig : unsigned ( 2 downto 0);

begin

process ( clk, reset_bar)

begin

if (reset_bar ='0' ) then

count_sig <= "000";

elsif falling_edge (clk) then

count_sig <= count_sig +1;

end if;

end process;

q<= std_logic_vector (count_sig);

end flow;

i can only do a up counter but not both up and down and also how do i put up to 2 digits?