Unused IO Banks

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If im not using any pins on a IO Bank do i need to connect up its IO VCC? or can i leave this bank completely un powered?

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Which device are you using?

FPGAs have a power-on-reset that will not release until the power rails are all within tolerance.

I'm not sure what flexibility there is in not having some VCCIO banks power up.

If you read the handbook and cannot quite figure it out, you could always start removing power from VCCIO banks on a development board and see if the FPGA still works. Eg., the Terasic DE-115 has VCCIO jumpers on some of its banks, while other boards have resistors between their main power rails and the VCCIO banks.

Cheers,

Dave

im using the EP1C3T100C8N, but only actually using 14 IO pins so two banks are unused

I think i will power the other two banks any way, im not saving any thing by not powering them just a little bit extra routing lol

thanks for your reply :)

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im using the EP1C3T100C8N, but only actually using 14 IO pins so two banks are unused

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p253 has the statement I recall:

http://www.altera.com/literature/hb/cyc/cyc_c5v1.pdf

"Normal operation does not occur until both power supplies are in their

recommended operating range"

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I think i will power the other two banks any way, im not saving any thing by not powering them just a little bit extra routing lol

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That would be my advice.

Cheers,

Dave

You're welcome.

Another word of advice - make sure to connect the JTAG signals!

Cheers,

Dave

im going to be programming the fpga using a micro controller when the board boots up, so no need for JTAG. although would you recommend having a header any way just incase?

can you have a fpga hooked upto a JTAG header and connected to a micro controller(for loading the bit file) at the same time?

Im very new to FPGAs

im currently using 'PS Configuration Circuit with a Microprocessor' from the doc 'AN 250: Configuring Cyclone FPGAs'

but it would be nice to add a JTAG header to that system as well so i can quickly test new designs, and only use the boot off the micro controller once im happy and the board works standalone

can the two be combined? i had a quick read of the AN 250 doc but could not find any examples of boot from micro controller combined with JTAG or AS header :(

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but it would be nice to add a JTAG header to that system as well so i can quickly test new designs, and only use the boot off the micro controller once im happy and the board works standalone

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Yes, so you have already answered the question yourself.

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can the two be combined? i had a quick read of the AN 250 doc but could not find any examples of boot from micro controller combined with JTAG or AS header

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JTAG configuration and debugging functions are available in any configuration mode. AS mode is alternative to PS. You need switches or jumpers for MSEL to select between both.

Im with you.

Thanks :)

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im going to be programming the fpga using a micro controller when the board boots up, so no need for JTAG. although would you recommend having a header any way just incase?

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The JTAG interface is;

1) A programmer

2) A communications interface

3) A logic analyzer interface

4) A NIOS processor debugger interface

5) A custom JTAG interface

.... and many more

The passive serial interface is *only* a programmer interface. You need it to program you device at power on. The JTAG interface is for all the problems you haven't thought of yet :)

Cheers,

Dave

I have added it hehe :)

If you dont mind could you have a quick look at my schematic and see if i have made any simple mistakes / missing any thing.

The design is a basic LPC2103 micro controller that configures the FPGA in PS mode at boot.

The LPC2103 also has a simple 8bit bus to the FPGA to send it bytes of data.

the FPGA just has 6 outputs to a simple pcb header

very simple design hehe :)