tx_bonding_clocks in ATX PLL and RapidIO IP Core

Question

Hi,In my design I instantiate a 4X RapidIO Core and a ATX PLL IP Core. According to Table 12 in RapidIO user guide, I should connect the 24-bit tx_bonding_clocks of ATX PLL to tx_bonding_clocks_chN of RapidIO IP Core( where N=0~3) respectively.But currently I can only generate a 6-bit tx_bonding_clocks in ATX PLL, and the signal definition of tx_bonding_clocks in XCVR PHY user guide is fixed 6-bit.So I connect tx_bonding_clocks_ch0 of ATX PLL to tx_bonding_clocks_ch0~3 of RapidIO IP core, then I got timing analysis errors.Any suggestion? How can I generate a ATX PLL IP core with 24-bit tx_bonding_clocks?Thanks, regards.

cheepinc_altera · Answer

Hi Yiwen,

I would like to apologize for the delay in response. It seems like I encounter some issues with notification reaching my mailbox. Sorry for the inconvenience.

As I understand it, you have some inquiries related to the ATX PLL bonding clock connection to the rapidIO IP. For your information, each ATX PLL will have fixed 6 bit width for tx_bonding_clocks output bus. Since you are using a single ATX PLL to drive RapidIO x 4, you use the same ATX PLL 6 bit output bus to drive all the 4 RapidIO bonding clock input bus.

Please let me know if there is any concern. Thank you.

Best regards,
Chee Pin

syiwe · Answer

Thanks.But according to the user guide, I should connect a 24-bit output ATX PLL to RapidIO x4.Or should I use 4 ATX PLLs to drive RapidIO x4?

cheepinc_altera · Answer

Hi,For your information, the ATX PLL tx_bonding_clocks is only of 6 bits. You would not be able to get 24 bits output. There seems to be some confusion with the RapidIO user guide. Thus, if you are using one ATX PLL, then you would need to connect the same bus of ATX PLL bonding clocks to all the 4 RapidIO channels bonding clock bus. If you are using 4 ATX PLLs, then you can connect each PLL separately to each channel of RapidIO.Please let me know if there is any concern. Thank you.Chee Pin

cheepinc_altera · Answer

Hi,Just would like to follow up with you on this. Thank you.

syiwe · Answer

Thank you for your answer.Currently I use a single ATX_PLL,  and how can I eliminate  the negative slacks in timing analysis in tx_bonding_clocks and rx_pma_clk clock region? (As you can see in the picture above).I already set the tx_bonding_clocks , txclk and rxclk as  global clock in assignment editor, the negative slack reduced to -0.371, still result in bit-error in data transmit and receive process.I will be appreciated if you can give me some suggestions.Thanks, regards.

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tx_bonding_clocks in ATX PLL and RapidIO IP Core

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