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SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

tx_bonding_clocks in ATX PLL and RapidIO IP Core

Hi, In my design I instantiate a 4X RapidIO Core and a ATX PLL IP Core. According to Table 12 in RapidIO user guide, I should connect the 24-bit tx_bonding_clocks of ATX PLL to tx_bonding_clocks_chN...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

Thanks for your update. I understand that you are using a single ATX PLL and connect the bonding clocks per the guideline. However, you still observe some timing violation.

Would you mind to help duplicating a new case specific on the timing negative slack and let me know the new case number? I would like to further engage our timing expert to provide further assistance on the timing closure.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin