Forum Discussion

Occasional Contributor

6 years ago

tx_bonding_clocks in ATX PLL and RapidIO IP Core

Hi, In my design I instantiate a 4X RapidIO Core and a ATX PLL IP Core. According to Table 12 in RapidIO user guide, I should connect the 24-bit tx_bonding_clocks of ATX PLL to tx_bonding_clocks_chN...

CheepinC_altera

Regular Contributor

6 years ago

Hi Yiwen, I would like to apologize for the delay in response. It seems like I encounter some issues with notification reaching my mailbox. Sorry for the inconvenience. As I understand it, you have some inquiries related to the ATX PLL bonding clock connection to the rapidIO IP. For your information, each ATX PLL will have fixed 6 bit width for tx_bonding_clocks output bus. Since you are using a single ATX PLL to drive RapidIO x 4, you use the same ATX PLL 6 bit output bus to drive all the 4 RapidIO bonding clock input bus. Please let me know if there is any concern. Thank you. Best regards, Chee Pin

SYiwe

Occasional Contributor

6 years ago

Thanks.

But according to the user guide, I should connect a 24-bit output ATX PLL to RapidIO x4.

Or should I use 4 ATX PLLs to drive RapidIO x4?

Forum Discussion

tx_bonding_clocks in ATX PLL and RapidIO IP Core

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