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SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

tx_bonding_clocks in ATX PLL and RapidIO IP Core

Hi, In my design I instantiate a 4X RapidIO Core and a ATX PLL IP Core. According to Table 12 in RapidIO user guide, I should connect the 24-bit tx_bonding_clocks of ATX PLL to tx_bonding_clocks_chN...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Just would like to follow up with you on this. Thank you.

  • SYiwe's avatar
    SYiwe
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Thank you for your answer.

    Currently I use a single ATX_PLL, and how can I eliminate the negative slacks in timing analysis in tx_bonding_clocks and rx_pma_clk clock region? (As you can see in the picture above).

    I already set the tx_bonding_clocks , txclk and rxclk as global clock in assignment editor, the negative slack reduced to -0.371, still result in bit-error in data transmit and receive process.

    I will be appreciated if you can give me some suggestions.

    Thanks, regards.