Transceiver Pseudo-CML equivalent circuit?

The other interesting thing that I observe, is that if I change VOD, I change the voltage swing, but not the common mode voltage, ie.,

1. VOD = 3 (default), Vhigh = 910mV, Vlow = 540mV, so Vcm = 725mV and Vpp = 370mV

2. VOD = 0, Vhigh = 800mV, Vlow = 660mV, so Vcm = 730mV and Vpp = 140mV

3. VOD = 7, Vhigh = 1100mV, Vlow = 330mV, so Vcm = 715mV and Vpp =770mV

So the common mode voltage is essentially unchanged.

If the transmitter was really only able to sink current, then as the sink current is increased, the Vlow voltage should get further from the Vhigh voltage, and the common-mode point should move lower. The observations show that changing VOD increases the peak-to-peak voltage, without changing the common mode voltage. Hence, the transmit buffer is not a simple CML source.

Cheers,

Dave

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Hence, the transmit buffer is not a simple CML source.

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Yes. What made you think, it would use unipolar current sources? It's not stated in the Altera documentation at any place.

The Altera documentation is suggesting a (differential) bipolar current source with programmable resistive termination. But I guess, you won't find implementation details. As with other FPGA OCT variants, there are most likely no physical resistors, just transistors. It's also not clear, if the PCML driver uses real current sources.

All you can rely on is the output voltage specification in the datasheet.

P.S.: Altera has filed patents related to FPGA IO structures. Particularly US2006220681 "Methods and Apparatus to DC Couple LVDS Driver to CML Level" may be interesting. US7855577 "Using a Single Buffer for Multiple I/O Standards" is also related to the topic.

A good place to search for patents and get the full text http://worldwide.espacenet.com

Hi FvM,

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What made you think, it would use unipolar current sources?

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Nothing really, I was just stating that the naive interpretation of Pseudo-CML driver as being like a CML driver was not correct, so was interested in a more correct definition :)

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It's not stated in the Altera documentation at any place.

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Yeah, I guess we can't expect it, since its part of Altera's secret recipe.

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The Altera documentation is suggesting a (differential) bipolar current source with programmable resistive termination. But I guess, you won't find implementation details. As with other FPGA OCT variants, there are most likely no physical resistors, just transistors. It's also not clear, if the PCML driver uses real current sources.

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That was the impression I was getting. I thought it confusing that the voltage between resistors was referred to as a common-mode voltage, when in fact its really a termination voltage. None of the signal measurements have a common mode equal to either the transmit Vcm or receive Vcm; unless of course I put a DC block in the signal path.

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All you can rely on is the output voltage specification in the datasheet.

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But even that is ambiguous. The termination voltages at the receiver are 820mV or 1100mV. There are comments in the DC switching characteristics chapter regarding the allowed common mode voltage as being within 10% of these values. However, from the measurements of the common mode voltages and peak-to-peak swings, these specifications are being violated by a GX-to-GX link, eg., Vcm ~ 730mV in all cases.

Table 1-23 on p1098 has the receiver characteristics. That table indicates that a voltage swing of 100mV would be an ok signal, but the common move appears to be limited to within 10% of the termination voltage. There are no comments on the sink/source current maximums for the transceiver pins.

I'm interested in whether the common mode can be shifted, and what the maximum currents are, as I have a PCML driver that is referenced to ground. A DC connection would result in current being sourced from the receiver, and the common mode shifting down. I can test an AC connection with this particular part (it has a PRBS spreader option), but I also want to investigate whether a DC connection is possible.

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P.S.: Altera has filed patents related to FPGA IO structures. Particularly US2006220681 "Methods and Apparatus to DC Couple LVDS Driver to CML Level" may be interesting. US7855577 "Using a Single Buffer for Multiple I/O Standards" is also related to the topic.

A good place to search for patents and get the full text http://worldwide.espacenet.com

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Ah-ha! Secret recipe ingredients. I'll check them out thanks!

Thanks for responding to this question.

Cheers,

Dave

Hi FvM,

US7924046 "Configurable emphasis for high-speed transmitter driver circuitry" describes transmitter circuits that are possibly the ones used in the Stratix devices. The transmit pre-emphasis circuits require current sources and sinks.

This helps me understand the operation of the transmitter.

Cheers,

Dave

Just to follow-up on the transmitter side of this discussion, the attached LTSpice circuit shows how two current sources at the transmitter can be used to get signal high/low voltages pretty close to those measured for the VOD default setting of 3, i.e., with 7.5mA current source, Vhigh = 920mV, Vlow = 550mV.

Cheers,

Dave

Hello Dave,

interesting. You see, that I didn't scan for all related Altera patents, I found I/O driver the stuff when looking for something different. The current switching topology refers to the standard design for LVDS drivers. It typically has no termination voltage source but a common mode voltage control loop, see the below schematic. You would be able to identify the actual implementation by dynamical measurements, because the common mode control loop would show a reduced bandwidth.

On the other hand, the schematic is still a simplification, because it has no programmable termination resistors.

Regards,

Frank

Hi Frank,

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I didn't scan for all related Altera patents

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No, I didn't think you had, but figured you might be interested in the patent I ended up finding.

Thanks for the hint to look at patents, I'll have to remember that in the future.

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I found I/O driver the stuff when looking for something different.

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I also found lots of other patents that will distract me from doing real work :)

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The current switching topology refers to the standard design for LVDS drivers. It typically has no termination voltage source but a common mode voltage control loop, see the below schematic. You would be able to identify the actual implementation by dynamical measurements, because the common mode control loop would show a reduced bandwidth.

On the other hand, the schematic is still a simplification, because it has no programmable termination resistors.

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Thanks. I'm happy with my simplified understanding of the transmitters now.

You don't happen to have any insight into the receiver common mode voltage range, and the current source capabilities of the receivers do you?

Cheers,

Dave

Hello Dave,

I must admit, that I've only limited experience with Altera gigabit transceivers. I did a PCIe customer project, but I'm more familiar with sub-gigabit LVDS interfaces. I try to keep informed about available technologies, however.

I notice, that utilizable receiver common mode voltages are speed dependant, you get optimal performance in a smaller range. Furthermore, they are affected by P,V,T variations. In so far, you can't but rely on specifications.

Regards,

Frank

Hi Frank,

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I must admit, that I've only limited experience with Altera gigabit transceivers. I did a PCIe customer project, but I'm more familiar with sub-gigabit LVDS interfaces. I try to keep informed about available technologies, however.

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Same here. My last design made a lot of use of the LVDS transceivers, but the FPGAs did not have the GXB blocks.

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I notice, that utilizable receiver common mode voltages are speed dependant, you get optimal performance in a smaller range. Furthermore, they are affected by P,V,T variations. In so far, you can't but rely on specifications.

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Where do you see that information? In the Stratix IV handbook, the only switching information I see is the stuff in Table 1-23 on pages 1096 to 1104 of the PDF. p1098 has the receiver details. Nothing in there about common mode changes that are speed dependent. The Stratix IV devices have a "Receiver buffer and CDR offset cancellation" mode where they should take care of PVT changes. I suspect if I try a DC connection where I draw too much current from the receivers, that this stuff won't work properly. I'm not planning on trying it, as I do not want to damage the FPGA.

Cheers,

Dave

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I suspect if I try a DC connection where I draw too much current from the receivers, that this stuff won't work properly. I'm not planning on trying it, as I do not want to damage the FPGA.

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Thank you for all your disscusion on this issue. Based on your experiment results and your helpful replies, I also draw some schematic and did simulaion using PSPICE, and now I have the same opion with you that the Transimitter output buffer is constructed similar to LVDS buffer, for both of them are sourcing differential current throught both of the differential pins at the same time. But I really want to know the maxium sink/source current capability of transimit termination resistors, because I want to terminate the transimit signals using standard 1.5-V CML termination method at the receiver end (the receiver is a programmable delay chip), which will give about a maxium of 12mA sink current through the internal termination resister in ArriaII GX. I really would like to know whether this 12mA current will damage the output buffer of transimitter in FPGA?

Thank you!

Dajun Huang