Honored Contributor
Honored ContributorHi FvM,
--- Quote Start --- What made you think, it would use unipolar current sources? --- Quote End --- Nothing really, I was just stating that the naive interpretation of Pseudo-CML driver as being like a CML driver was not correct, so was interested in a more correct definition :) --- Quote Start --- It's not stated in the Altera documentation at any place. --- Quote End --- Yeah, I guess we can't expect it, since its part of Altera's secret recipe. --- Quote Start --- The Altera documentation is suggesting a (differential) bipolar current source with programmable resistive termination. But I guess, you won't find implementation details. As with other FPGA OCT variants, there are most likely no physical resistors, just transistors. It's also not clear, if the PCML driver uses real current sources. --- Quote End --- That was the impression I was getting. I thought it confusing that the voltage between resistors was referred to as a common-mode voltage, when in fact its really a termination voltage. None of the signal measurements have a common mode equal to either the transmit Vcm or receive Vcm; unless of course I put a DC block in the signal path. --- Quote Start --- All you can rely on is the output voltage specification in the datasheet. --- Quote End --- But even that is ambiguous. The termination voltages at the receiver are 820mV or 1100mV. There are comments in the DC switching characteristics chapter regarding the allowed common mode voltage as being within 10% of these values. However, from the measurements of the common mode voltages and peak-to-peak swings, these specifications are being violated by a GX-to-GX link, eg., Vcm ~ 730mV in all cases. Table 1-23 on p1098 has the receiver characteristics. That table indicates that a voltage swing of 100mV would be an ok signal, but the common move appears to be limited to within 10% of the termination voltage. There are no comments on the sink/source current maximums for the transceiver pins. I'm interested in whether the common mode can be shifted, and what the maximum currents are, as I have a PCML driver that is referenced to ground. A DC connection would result in current being sourced from the receiver, and the common mode shifting down. I can test an AC connection with this particular part (it has a PRBS spreader option), but I also want to investigate whether a DC connection is possible. --- Quote Start --- P.S.: Altera has filed patents related to FPGA IO structures. Particularly US2006220681 "Methods and Apparatus to DC Couple LVDS Driver to CML Level" may be interesting. US7855577 "Using a Single Buffer for Multiple I/O Standards" is also related to the topic. A good place to search for patents and get the full text http://worldwide.espacenet.com --- Quote End --- Ah-ha! Secret recipe ingredients. I'll check them out thanks! Thanks for responding to this question. Cheers, Dave
