Honored Contributor
Honored ContributorHi Frank,
--- Quote Start --- I must admit, that I've only limited experience with Altera gigabit transceivers. I did a PCIe customer project, but I'm more familiar with sub-gigabit LVDS interfaces. I try to keep informed about available technologies, however. --- Quote End --- Same here. My last design made a lot of use of the LVDS transceivers, but the FPGAs did not have the GXB blocks. --- Quote Start --- I notice, that utilizable receiver common mode voltages are speed dependant, you get optimal performance in a smaller range. Furthermore, they are affected by P,V,T variations. In so far, you can't but rely on specifications. --- Quote End --- Where do you see that information? In the Stratix IV handbook, the only switching information I see is the stuff in Table 1-23 on pages 1096 to 1104 of the PDF. p1098 has the receiver details. Nothing in there about common mode changes that are speed dependent. The Stratix IV devices have a "Receiver buffer and CDR offset cancellation" mode where they should take care of PVT changes. I suspect if I try a DC connection where I draw too much current from the receivers, that this stuff won't work properly. I'm not planning on trying it, as I do not want to damage the FPGA. Cheers, Dave
