Transceiver Pseudo-CML equivalent circuit?

--- Quote Start ---

I suspect if I try a DC connection where I draw too much current from the receivers, that this stuff won't work properly. I'm not planning on trying it, as I do not want to damage the FPGA.

--- Quote End ---

Thank you for all your disscusion on this issue. Based on your experiment results and your helpful replies, I also draw some schematic and did simulaion using PSPICE, and now I have the same opion with you that the Transimitter output buffer is constructed similar to LVDS buffer, for both of them are sourcing differential current throught both of the differential pins at the same time. But I really want to know the maxium sink/source current capability of transimit termination resistors, because I want to terminate the transimit signals using standard 1.5-V CML termination method at the receiver end (the receiver is a programmable delay chip), which will give about a maxium of 12mA sink current through the internal termination resister in ArriaII GX. I really would like to know whether this 12mA current will damage the output buffer of transimitter in FPGA?

Thank you!

Dajun Huang