Altera_Forum
Honored Contributor
Honored ContributorTotal execution time and propagation delay
hi,
How to calculate total execution time and propagation delay for VHDL files under Quartus II? Thank youForum Discussion
21 Replies
Altera_ForumIf you aren't familiar with the tools or the code you're dealing with, probably the easiest and simplest way is to run a ModelSim simulation and treat it like a black box: apply known inputs and wait for known outputs to show up.
- Altera_Forum
Thank you, for your reply.
Kindly note that, I have 3 inputs 256 bit each which takes a long time under modelsim to simulate it. I am looking for a short way to calculate execution time and propagation delay. I got the Fmax, but what are the equations that I should apply in order to get execution time and propagation. - Altera_Forum--- Quote Start --- Hello aaabbb, I have same problem, have you any ideas how to calculate the total time and propagation delay on Quartus II? Thank you --- Quote End --- The timing analyser will ensure that your design meets the timing specifications that you give it. Assuming you mean latency when you refer to "execution time", then you can easily work this out from the number of registers in the pipeline.
- Altera_Forum--- Quote Start --- The timing analyser will ensure that your design meets the timing specifications that you give it. Assuming you mean latency when you refer to "execution time", then you can easily work this out from the number of registers in the pipeline. --- Quote End --- Hi Tricky, Thank you for your answer. I have, for example, an adder 4 bits and i want to calculate the "hardware execution time" for this adder. After compiling the code, and by using "TimeQuest Timing Analyser", i got the attached "Propagation Delay". Knowing that the total "propagation delay" is taken as the "hardware execution time", how to calculate the total "propagation delay"? In the attached file, i have RR=RF=FF=FR, is it normal?? Best Regards,
- Altera_Forum
This is not a execution time, this is the propogation delay through this circuit for this compilation in the worst case scenario. Next time you compile the code, this will change. Timequest is only meant to tell you if your design met the timing specs that you specified or if it missed. It is meant for synchronous designs only. Relying on propagation delays through the device is NOT reliable, as they will be affected by PVT (process voltage and temperature) ie. as the temperature changes, so will the propogation delay. To mitigate this you use a synchronous circuit, then you know what the register-register timing is, and timequest can tell you if your design can meet it.
- Altera_Forum--- Quote Start --- This is not a execution time, this is the propogation delay through this circuit for this compilation in the worst case scenario. Next time you compile the code, this will change. Timequest is only meant to tell you if your design met the timing specs that you specified or if it missed. It is meant for synchronous designs only. Relying on propagation delays through the device is NOT reliable, as they will be affected by PVT (process voltage and temperature) ie. as the temperature changes, so will the propogation delay. To mitigate this you use a synchronous circuit, then you know what the register-register timing is, and timequest can tell you if your design can meet it. --- Quote End --- Thank you Tricky, you are right. If the "Total Propagation Delay" is not a "Hardware Execution Time", so how to calculate the "Hardware Execution Time" of my adder 4-bits. The code of an adder 4-bits is attached. Best Regards,
- Altera_Forum
There is no such thing as "hardware execution time".
You have no clock in your design, so the circuit will have a propogation delay as I described previously. if you had a clock in the design, then you could calculate the latency. - Altera_Forum--- Quote Start --- There is no such thing as "hardware execution time". You have no clock in your design, so the circuit will have a propogation delay as I described previously. if you had a clock in the design, then you could calculate the latency. --- Quote End --- I would like to calculate the time required to execute this adder in hardware(FPGA) and in Nios ii. have you any proposition to do this??
- Altera_Forum--- Quote Start --- I would like to calculate the time required to execute this adder in hardware(FPGA) and in Nios ii. have you any proposition to do this?? --- Quote End --- With the current code, that is impossible as it is an asynchronous (no clock) process Make it synchronous, and then you will know the latency ie. how many clocks are required to complete the operation.
- Altera_Forum--- Quote Start --- With the current code, that is impossible as it is an asynchronous (no clock) process Make it synchronous, and then you will know the latency ie. how many clocks are required to complete the operation. --- Quote End --- When i add a clock in my code i get a negative slack. I searched how to avoid this problem but i haven't found.
