Honored ContributorI am implementing a RS232 controller on FPGA. I have the Verilog code for transmitter and reciever. can anyone give the details how to extract the state diagrams or state machines from this code. I am using Quartus II sofware. I attached code too.
Honored Contributorhave you tried going to Tools => Netlist Viewers => State Machine Viewer after doing Analysis and Elaboration?
Honored ContributorHi, I tired but it shows the message "Design has no state machine". could u help me out
Honored ContributorIt is quite easy to extract manually the state machine design in this code. Just have a look at the case(state) statements.
I'm not sure, but the state machine may not be recognized by Quartus because there is no reset state. I could be wrong though. That said you should really add a reset state to this code. Nothing here tells how the fsm should start.Honored Contributorcould u please add the reset state in that code and send it to me. If we cant generate in quartus, is there anyother software to generate the state machine.
Honored ContributorI don't know Verilog well enough to be sure to post correct code, but I'm sure any good Verilog book has lots of examples for FSM's.
The problem isn't that Quartus doesn't synthesize your code. It should still compile and run on an FPGA. It is just that your code doesn't seem to be recognized as a state machine, and as such isn't optimized and can't be shown in the state machine viewer.Honored ContributorI shall I translate it to other language like VHDL,C. so that u can correct the code.
Honored ContributorHonored ContributorHello all!
I don't want create new topic with my problem (like this). I did simple Write-Read RSR232 design by using two files from this topic (аsync_receivеr.v and аsync_trаnsmitter.v). But some (0-3) first symbols from COM-port are wrong:( Where is my error? Who helps me? Thanks all! P.S.: Quartus 9_1 design is "RS_Test.zip" P.P.S.: VS'2008 design is "com.zip"
