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Altera_Forum
Honored Contributor
Honored Contributorto extract state diagrams from vhdl/verilog code
I am implementing a RS232 controller on FPGA. I have the Verilog code for transmitter and reciever. can anyone give the details how to extract the state diagrams or state machines from this code. I a...
Altera_ForumHonored Contributor
Honored ContributorI shall I translate it to other language like VHDL,C. so that u can correct the code.
