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Altera_Forum
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16 years ago

to extract state diagrams from vhdl/verilog code

I am implementing a RS232 controller on FPGA. I have the Verilog code for transmitter and reciever. can anyone give the details how to extract the state diagrams or state machines from this code. I a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hello all!

I don't want create new topic with my problem (like this).

I did simple Write-Read RSR232 design by using two files from this topic (аsync_receivеr.v and аsync_trаnsmitter.v).

But some (0-3) first symbols from COM-port are wrong:(

Where is my error? Who helps me?

Thanks all!

P.S.: Quartus 9_1 design is "RS_Test.zip"

P.P.S.: VS'2008 design is "com.zip"