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Altera_Forum
Honored Contributor
Honored Contributorto extract state diagrams from vhdl/verilog code
I am implementing a RS232 controller on FPGA. I have the Verilog code for transmitter and reciever. can anyone give the details how to extract the state diagrams or state machines from this code. I a...
Altera_ForumHonored Contributor
Honored ContributorIt is quite easy to extract manually the state machine design in this code. Just have a look at the case(state) statements.
I'm not sure, but the state machine may not be recognized by Quartus because there is no reset state. I could be wrong though. That said you should really add a reset state to this code. Nothing here tells how the fsm should start.
