Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

to extract state diagrams from vhdl/verilog code

I am implementing a RS232 controller on FPGA. I have the Verilog code for transmitter and reciever. can anyone give the details how to extract the state diagrams or state machines from this code. I a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I don't know Verilog well enough to be sure to post correct code, but I'm sure any good Verilog book has lots of examples for FSM's.

The problem isn't that Quartus doesn't synthesize your code. It should still compile and run on an FPGA. It is just that your code doesn't seem to be recognized as a state machine, and as such isn't optimized and can't be shown in the state machine viewer.