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Altera_Forum
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16 years ago

to extract state diagrams from vhdl/verilog code

I am implementing a RS232 controller on FPGA. I have the Verilog code for transmitter and reciever. can anyone give the details how to extract the state diagrams or state machines from this code. I a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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I shall I translate it to other language like VHDL,C. so that u can correct the code.

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Hi,

I found the root cause why the statemachine extraction fails. It is not allowed to access the state value with an index.

// if(Baud8Tick && next_bit && state[3]) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};

For testing I changed the line to :

if(Baud8Tick && next_bit && state==4'b1001) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};

I have a small project attached.

Kind regards

GPK