Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorto extract state diagrams from vhdl/verilog code
I am implementing a RS232 controller on FPGA. I have the Verilog code for transmitter and reciever. can anyone give the details how to extract the state diagrams or state machines from this code. I a...
Altera_ForumHonored Contributor
Honored Contributorcould u please add the reset state in that code and send it to me. If we cant generate in quartus, is there anyother software to generate the state machine.
