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manpreet_1604's avatar
manpreet_1604
Icon for New Contributor rankNew Contributor
4 years ago

Timing Requirements not met

Hi All,

I am using Altera CPLD "EPM7064" as a Replacement of Atmel "ATF1504" the original code was generated and tested for ATF1504 in "pro chip designer tool" using Verilog, when the same code is compiled in Quartus II Version 13.00 it get compiled but with 11 warning msg if I ignore them and Burn the generated pof file in Chip it is working but having some issue when compared to Orignal code generated for ATF1504

And the Interesting and confusing part is that If I use pof to jed conversion tool and convert the same pof file generated for Altera IC and convert it to Jed for Atmel IC and burn into Atmel ATF1504 it is working fine without any issue.

Is that a hardware issue or Altera is malfunctioning due to its warning msg

I read about the warning and find that I have to provide .sdc constrain file so I write 2 constrain in it as mentioned bellow

  1. create_clock -period 17857.142857143 {get_ports pulse}
  2. create_clock -period 17857.142857143 {get_ports pwmin2}

As my pulse ( mail clock ) is driving on 56khz

still have the same issue and some warning

Please find the complete details in the attached doc file

5 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    1) Do you have top-level I/O ports named "pulse" and "pwmin2"? The warnings are saying your .sdc is not finding these ports.

    2) You can safely ignore the parallel compilation warning. I doubt a design like this takes a long time to compile.

    3) The latch warning is because you are probably improperly coding registers. Can you share some code?

  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    Does the above reply help? Otherwise, can you share some code?


    Regards,

    Nurina


  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    We did not receive any response to the previous reply provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.


    P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!

    Regards,

    Nurina


  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    That is not how to define a flipflop. That's why you're getting latches. You need a clock signal (clk) and it should be something like this:

    always @(posedge clk or posedge reset)
   begin
       if (reset)
          outflip = 0;
       else
          outflip = in;
   end
assign out = outflip;
endmodule

    "in" cannot be both an input and a clock to create a flipflop.