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manpreet_1604's avatar
manpreet_1604
Icon for New Contributor rankNew Contributor
3 years ago

Timing Requirements not met

Hi All, I am using Altera CPLD "EPM7064" as a Replacement of Atmel "ATF1504" the original code was generated and tested for ATF1504 in "pro chip designer tool" using Verilog, when the same code is...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

That is not how to define a flipflop. That's why you're getting latches. You need a clock signal (clk) and it should be something like this:

always @(posedge clk or posedge reset)
   begin
       if (reset)
          outflip = 0;
       else
          outflip = in;
   end
assign out = outflip;
endmodule

"in" cannot be both an input and a clock to create a flipflop.