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manpreet_1604's avatar
manpreet_1604
Icon for New Contributor rankNew Contributor
3 years ago

Timing Requirements not met

Hi All, I am using Altera CPLD "EPM7064" as a Replacement of Atmel "ATF1504" the original code was generated and tested for ATF1504 in "pro chip designer tool" using Verilog, when the same code is...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

1) Do you have top-level I/O ports named "pulse" and "pwmin2"? The warnings are saying your .sdc is not finding these ports.

2) You can safely ignore the parallel compilation warning. I doubt a design like this takes a long time to compile.

3) The latch warning is because you are probably improperly coding registers. Can you share some code?