module flipflop(in,out,reset);
    input in;
    input reset;
    output out;
    //reg out;
	reg outflip;
	wire out;
	    
  always @(posedge in or posedge reset)
  begin
  if (reset)
  outflip = 0;
  else
  outflip =1;
  end
  assign out = outflip & in; 
  endmodule