Forum Discussion
Sumanth
Occasional Contributor
9 months agoTiming Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I expe...
Sumanth
Occasional Contributor
7 months agoPlease find the below signal tap waveform
The PLL locked signal is used as a reset for the Remote Update IP after inversion, and the reset is extended and synchronized for five additional cycles of the Remote Update clock. Later, a state machine checks that the busy signal is not asserted. Once busy is deasserted, it attempts to read the current configuration boot address and then the reconfiguration trigger condition. For all read operations, a response of all 1’s was observed.
- Farabi_Altera7 months ago
Regular Contributor
Hello,
Could you please explain what is the expected behavior you observed, and what is the not expected behavior you observed?
regards,
Farabi