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Sumanth's avatar
Sumanth
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2 months ago

Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)

I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I expe...
Configuration
Core Logic
Programmable Logic Device
Sumanth's avatar
Sumanth
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28 days ago

In the official Remote Update IP design example, the reset command waits for 0.6 seconds and then performs the read or write operations. Between each read or write operation, it waits for 0.6 seconds before proceeding with further read or write operations.

Note: The official Remote Update IP functions correctly on both boards (10CX150YF672E5G and 10CX105YF672I5G).

In my design, I wait for the busy signal to deassert before performing any further read or write operations.

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    27 days ago

    Hi Sumanth,

    Thanks for confirming. Since the example works on both devices, the IP is consistent. The difference I'm assuming seems related to timing in your design.
    Could you please try adding a short delay after reset or between operations and see if it helps.

    Let me know the result.

    Best regards,
    Fakhrul