Time Quest analyzer questions

That is a large slack. It is likely the cause of strange results you got. A design must meet timing to work reliably.

Divide and sqrt are complex functions to complete in 1 clock. Did you implement it using comb logics? A lot of ALUTs but almost no registers? The circuit is inefficient by design if so. You may want to redesign the divide and sqrt. Quick and dirty way would be to insert more pipelines along the comb logics.

Another quick workaround would be to make the logics multi-cycle, i.e. observing the result after the delay. Keep the inputs static throughout.

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Hello guys..

I've almost finished my project. In this project I have a design partition reporting a negative slack of about -41ns (I use clocks of 75MHz and 150MHz). Now every time I compile my project and then program the FPGA I see strange result on the spectrum scope.

The fact that I have these strange results may be due to the not met timing requirements ?

Using the time analyzer and running the report timing tab, I see that the negative slack is relative to two nodes I have in my design : the sqrt node and the divide node. I have pipelined these nodes with 1 clock period.

My design is something like:

--> input1[31..0] --> sqrt(input[31..0])=sqrt[15..0] --> divide(input2[31..0],sqrt[15..0])

The time analyzer says that there is a data delay of about 55.

How can I solve this issue ? (I'm a novice in time requirements)

Thank you for your time.

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I understand from this post and previous ones that you want to equalise two signals to same power.

the following sequence may help simplify design:

get mean power1 (32 bits) => square root(power1) as 15 bits, call it (a)

and same for power2 => square root(power2) as 15 bits, call it (b)

now divide a/b as multiplication of a * 1/b using look up table for 1/b

b value will address the table and content should be 1/b

the range of b is 0:32767 and if have step of 100 then 328 memory depth will cover well.

thus you need to find out values for 1/(0:100:32767), scale them say by 2^10, multiply by (a) and discard 10 bits.

Thank you all for your replies !!

@kaz:

This time I'm not trying to equalise two signals to same power. The operation of dividing and scaling is done with a NiosII processor. By the way your point is really interesting. I will keep it in mind.

@tricky and @tzestan

Yes I'm using the altera standard cores. If I set a pipeline = 10 for the sqrt and divide operations means that I have the first useful output after EVERY 10 clock periods or that I have ONLY a first delay of 10 and then every input produce an useful output ?

Thank you !

Thank you tricky..

So it means that if my pipe length is 3 :

[ai bi ci di ei] --> [U U U ao bo co do eo]

Am I right ??

Thank you for your help !