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Altera_Forum
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11 years ago

Time Quest analyzer questions

Hello guys.. I've almost finished my project. In this project I have a design partition reporting a negative slack of about -41ns (I use clocks of 75MHz and 150MHz). Now every time I compile m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

as the above poster said, the easiest way is increased pipelining. Are you using Altera divide and sqrt cores? At those frequencies and word widths, you're going to need longish pipelines of >10 clocks each to meet the timing requirements.