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Altera_Forum's avatar
Altera_Forum
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12 years ago

Time Quest analyzer questions

Hello guys.. I've almost finished my project. In this project I have a design partition reporting a negative slack of about -41ns (I use clocks of 75MHz and 150MHz). Now every time I compile m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The latency means you have to wait 10 clocks from an input to an output. So for N inputs with pipeline length of 10, you need a total of N + 10 clocks to complete all N calculations. But with more pipelining, you can increase the clock speed, increasing the throughput.