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Altera_Forum
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12 years ago

Time Quest analyzer questions

Hello guys.. I've almost finished my project. In this project I have a design partition reporting a negative slack of about -41ns (I use clocks of 75MHz and 150MHz). Now every time I compile m...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Thank you all for your replies !!

@kaz:

This time I'm not trying to equalise two signals to same power. The operation of dividing and scaling is done with a NiosII processor. By the way your point is really interesting. I will keep it in mind.

@tricky and @tzestan

Yes I'm using the altera standard cores. If I set a pipeline = 10 for the sqrt and divide operations means that I have the first useful output after EVERY 10 clock periods or that I have ONLY a first delay of 10 and then every input produce an useful output ?

Thank you !