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Altera_Forum's avatar
Altera_Forum
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12 years ago

Time Quest analyzer questions

Hello guys.. I've almost finished my project. In this project I have a design partition reporting a negative slack of about -41ns (I use clocks of 75MHz and 150MHz). Now every time I compile m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

That is a large slack. It is likely the cause of strange results you got. A design must meet timing to work reliably.

Divide and sqrt are complex functions to complete in 1 clock. Did you implement it using comb logics? A lot of ALUTs but almost no registers? The circuit is inefficient by design if so. You may want to redesign the divide and sqrt. Quick and dirty way would be to insert more pipelines along the comb logics.

Another quick workaround would be to make the logics multi-cycle, i.e. observing the result after the delay. Keep the inputs static throughout.