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Altera_Forum
Honored Contributor
12 years agoTime Quest analyzer questions
Hello guys.. I've almost finished my project. In this project I have a design partition reporting a negative slack of about -41ns (I use clocks of 75MHz and 150MHz). Now every time I compile m...
Altera_Forum
Honored Contributor
12 years agoThat is correct. You just have the initial wait period. If your input is bursty, just create a valid flag to sit alongside the data, pipelined to the correct length.