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Hello guys..
I've almost finished my project. In this project I have a design partition reporting a negative slack of about -41ns (I use clocks of 75MHz and 150MHz). Now every time I compile my project and then program the FPGA I see strange result on the spectrum scope.
The fact that I have these strange results may be due to the not met timing requirements ?
Using the time analyzer and running the report timing tab, I see that the negative slack is relative to two nodes I have in my design : the sqrt node and the divide node. I have pipelined these nodes with 1 clock period.
My design is something like:
--> input1[31..0] --> sqrt(input[31..0])=sqrt[15..0] --> divide(input2[31..0],sqrt[15..0])
The time analyzer says that there is a data delay of about 55.
How can I solve this issue ? (I'm a novice in time requirements)
Thank you for your time.
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I understand from this post and previous ones that you want to equalise two signals to same power.
the following sequence may help simplify design:
get mean power1 (32 bits) => square root(power1) as 15 bits, call it (a)
and same for power2 => square root(power2) as 15 bits, call it (b)
now divide a/b as multiplication of a * 1/b using look up table for 1/b
b value will address the table and content should be 1/b
the range of b is 0:32767 and if have step of 100 then 328 memory depth will cover well.
thus you need to find out values for 1/(0:100:32767), scale them say by 2^10, multiply by (a) and discard 10 bits.
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