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david850128's avatar
david850128
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5 days ago

Subject: Issues Implementing Hitless Update on MAX 10 via Quartus Prime Programmer (AN904)

Target Devices: 10M08SAU324I7G / 10M25SAU324I7G

Reference Document: Intel AN904 (Section 1.5: Implementing Hitless Update using Intel Quartus Prime Programmer)

Problem Description:

We are following the guidelines in AN904 (Section 1.5) to implement a Hitless Update on a MAX 10 FPGA using Intel Quartus Prime Programmer along with an .ips file for ISP CLAMP settings.

We have successfully created (Creating IPS File) and loaded (Executing IPS File) the .ips file. However, during flashing tests, we are unable to achieve a true hitless update (i.e., updating and activating the new firmware live without disrupting active logic execution).

Depending on the Programmer settings, we observed two distinct behaviors:

Test Scenarios & Results

Scenario 1: "Enable real-time ISP to allow background programming" is UNCHECKED

Result & Behavior:

The new firmware (FW) takes effect after programming completes, but the process is NOT hitless. Since the 10M25 FPGA controls the board's power sequencing (PWR SEQ), the FPGA logic stops running during programming, triggering an unintended system/machine reboot.

Scenario 2: "Enable real-time ISP to allow background programming" is CHECKED

Result & Behavior:

Background programming finishes successfully without interrupting system operation. However, the new firmware does NOT take effect immediately. A manual Power-On Reset (POR) / power cycle is required for the new firmware image to actually load and run.

Questions

1.Is there any key step or setting missing in our Quartus Programmer setup or workflow?

2.When Real-time ISP is enabled, how can we properly trigger an internal reconfiguration after programming completes, so that the new image loads immediately while the I/O pins remain clamped (Hitless)?

3.Please let us know if any additional details, logs, or project configurations are needed to help diagnose this issue.

Thank you in advance for your support!

Configuration
Programmable Logic Device

1 Reply

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    1 hour ago

    Hi David,
     

    Thank you for the detailed explanation.

    The behavior you observed is consistent with MAX 10 operation. With Real-Time ISP enabled, the existing design continues running while the internal flash is programmed. However, the new image becomes active only after the next reconfiguration cycle, such as POR or an nCONFIG trigger. This explains Scenario 2.

     

    Please note one important limitation: hitless update does not mean that the existing user logic continues executing during reconfiguration. It means that specified I/O states can be maintained while the device changes to the new image.

    For the POF+IPS Programmer flow:

    • With Real-Time ISP enabled, background programming is performed, but ISP Clamp is skipped.
    • With Real-Time ISP disabled, the .ips clamp states are applied, but the active logic stops during programming.

    Therefore, there is no additional Programmer setting that combines continuous logic operation, .ips clamping and immediate image activation in this flow.

     

    If maintaining the PWR SEQ output states during reconfiguration is the requirement, please use the AN904 JAM/JBC or external-JTAG hitless-update flow. Issuing PULSE_NCONFIG alone triggers reconfiguration but does not ensure that the .ips states remain clamped.

    Relevant references:


    Regards,
    Fakhrul