Subject: Issues Implementing Hitless Update on MAX 10 via Quartus Prime Programmer (AN904)

Hi David,
 

Thank you for the detailed explanation.

The behavior you observed is consistent with MAX 10 operation. With Real-Time ISP enabled, the existing design continues running while the internal flash is programmed. However, the new image becomes active only after the next reconfiguration cycle, such as POR or an nCONFIG trigger. This explains Scenario 2.

Please note one important limitation: hitless update does not mean that the existing user logic continues executing during reconfiguration. It means that specified I/O states can be maintained while the device changes to the new image.

For the POF+IPS Programmer flow:

• With Real-Time ISP enabled, background programming is performed, but ISP Clamp is skipped.
• With Real-Time ISP disabled, the .ips clamp states are applied, but the active logic stops during programming.

Therefore, there is no additional Programmer setting that combines continuous logic operation, .ips clamping and immediate image activation in this flow.

If maintaining the PWR SEQ output states during reconfiguration is the requirement, please use the AN904 JAM/JBC or external-JTAG hitless-update flow. Issuing PULSE_NCONFIG alone triggers reconfiguration but does not ensure that the .ips states remain clamped.

Relevant references:

• AN904: MAX 10 Hitless Update Implementation Guidelines
• KDB 000080468

Regards,
Fakhrul