Hi I have been working on DE3 board with the above mentioned FPGA for some months now. I am trying to deserialize 8 LVDS channels from an ADC. each channel is 12 bits and ADC can work upto 50 Mega Samples per second. I am designing my own Deserializing circuit because there are not enough PLLs on DE3 FPGA ( i will interfacing 12 ADCs where as there are only 8 PLLs on FPGA) and each SERDES Megafunction requires 1 PLL. I am trying to operate IO pins at (max) 600 Mbits per second and my shift registers are working at half the bit rate i.e. 300 mega shifts per seconed (as each channel has 2 shift registers, 1 for even stream of bits and other one for odd. In the end i interleave two streams). I have tried many different design approaches along with playing arround with chip planner defining regions, assigning specific resources to different instances and so on... but each of my design fails at arround 25 Mega Samples. Simulation shows a picture perfect scenario even at 50 MHz. I was wondering if IO pins are creating the bottle neck here or is it the shift registers in my design. ( i am using LPM_SHIFTREG megafunction for shift registers) If anyone can provide me some idea about where the problem could be, i would be greatful.

I don't think, that you need a PLL for each ADC. You may use a PLL output for each ADC, if you want to adjust the receiving phase for each ADC individually, which shouldn't be necessary normally. At least, you should provide a common phase adjustment for the fast SERDES clock (300 MHz) for all ADCs. Alternatively, you can use the bitclock output from ADC as SERDES clock and no PLL at all. Personally, I prefer the PLL variant. The SERDES should use an altddio_in block as 1:2 demux. Than a single SR, shifting in two bits for each fastclock edge, can be used. It has no problem to achieve 600 MBPS rate with CIII. A user designed SERDES can provide deserialization factors, that aren't directly supported by the altlvds MegaFuntion with CIII, e.g. 12 and 14. It also allows a clearer configuration of timing parameters. P.S.: Utilizing the test pattern option of LVDS ADC and PLL dynamic phase shift, an automatic SERDES phase calibration can be realized.

Hi FvM, Unfortunately i cant use 1 PLL with multiple ADCs as each ADC is on a separate board with its own connector. I have designed a Back Plane PCB which splits each HSTC Connector's IO pins only (no dedicated clock pins) to 3 small connectors (for 3 ADC). Thus 4 HSTCs provide me with 12 connectors for ADCs, none of which share pins on the FPGA. Also HSTC on DE3 has only 4 dedicated clock pins (thats y i didnt use them) and quartus wont let me connect PLL to a normal IO pin. "Alternatively, you can use the bitclock output from ADC as SERDES clock and no PLL at all." Well this might work. Only worry i have is if the Bitclock will have enough fanout to support SERDES as it is using a normal IO pin instead of a dedicated clock pin. EDIT "Hmmm. Just tried ALTLVDS megafunction. The slow clock has a dutycycle recuirement of 8.33%. One from my ADC is 50%. So i dont know if this approach will work..." Thanks

What speed grade device is on the DE3 board? 600Mbps on an input port is pretty fast, as you've only got a 1.666ns bit period. My second concern is that, being limited by the board you're using, a number of the clocks will be coming in on regular I/O. That means you're going to use local routing to get to all the I/O in the databus, which means the delay to every I/O will be different. If you're timing constraints are correct, then the Quartus II fitter will modify the delay chains on the input registers to center the data onto the clock edge, but it can only do so much. My third concern is that, without a PLL, you're raw clock delay variance will be too large. For example, let's say it takes 3ns for the clock to route to the I/O, which is pretty fast. That's 3ns in the slow corner timing model. In the fast corner model it could easily be half that, especially in the slowest speed grade, so that means your clock delay could vary between 1.5ns and 3ns over PVT, which is pretty much the whole data eye. I'm making these numbers up, but you get the point. A PLL's feedback loop is designed to eliminate PVT variance on the clock tree, which makes I/O timing on fast interfaces much more feasible. So I don't think it's a logical issue, but a timing issue, that will be the problem. I haven't built anythign up and tested it out, but have serious concerns. Let me know if any of that doesn't make sense.

Hey Rysc Well, it is a C3 speed grade device so it is not the fastest available. I agree completely with what you have said about routing and fitter. Unfortunately i cant use the luxury of PLLs in the device otherwise things would have been easier. Quoting "If you're timing constraints are correct, then the Quartus II fitter will modify the delay chains on the input registers to center the data onto the clock edge, but it can only do so much." Well this is where i am not sure if my timing constraints are right. Initially I was using classic timing analyzer because of its simplicity. Simulation showed things working even at IO rate of 600Mbps. When I tried TimeQuest timing analyzer ( and to be honest, guessed some of the constrains) the output got messed up. To get the valid constraints, i tried going through Device datasheets but a lot of stuff there was ambiguous and went over my head. Is getting the constraints right my only chance or i can try some thing different. It might sound crazy but someone suggested that i should try to get it to LUT level and implement stuff (equations!!!) there. I have no idea how to do that but again if all the problems are because of IO/clock missalignments due to different nonconstant delays, things in LUT will get messed up anyways... Regards

I didn't realize, that DE3 is using Stratix III rather than Cyclone III. The points I mentioned about user designed software SERDES are basically valid for Stratix III, that also has DDIO capabilities in IO cells. But there are also interesting options provided by the Stratix III hardware SERDES with DPA function. As you pointed out, you can't use individual PLLs with 12 ADC. As far as I see, there are some dedicated clock inputs at the HSTC connectors. So the SERDES can use either the ADC input clock inside the FPGA or the FCO from one ADC. The phase should be adjusted individually for each ADC. DPA would allow an adjustment of each individual ADC output. In this case, delay skew caused by DE3 board and external wiring could be cancelled.

Stratix III EP3SL340c3 Diffrential IO data rate

13 Replies

Altera_Forum
Honored Contributor
16 years ago
Your solution sounds somewhat complicated, you should be able to run the shift register at 240 MHz directly. If you are not able to operate the design faster than 480 MBPS, the issue is most likely related to timing and possibly signal quality of the LVDS input. Of course, the data must be transfered to the slow (frame) clock, but that's not very critical, I think.

I also suggested to use hardware SERDES (=ALTLVDS Megafunction) with FPGA internal reference clock and DPA. Did you try it?
Altera_Forum
Honored Contributor
16 years ago
As i mentioned above, to use ALTLVDS, either i needed to use an internal PLL or external clock source. The PCB i used to interface ADC with HSTC was only connected to IO pins and Quartus wont let me place a PLL to those IO pins. To use external clock source, i needed a 80 MHz frame clock with 16% duty cycle as it is required by ALTLVDS. (80 MHz instead of 40 because ALTLVDS does not support 12 bits and i needed to go for 6 bit serdes thus doubling the frame rate) this sort of clock was not available from my ADC and using a PLL was not an option open to me. i tried this as u suggested and as i UNDERSTOOD but couldnt get far as i had no idea how to synchronize internal clock with the bit stream coming from ADC with out using a PLL.

Also i can get my design to work upto 500Mbps which is the IO limit for my device( i think i read it in stratix III handbook). i am happy with 40 MHz ( 480 Mbps) as it does the job for me with the oscillator i have available on ADC, although my ADC can go upto 50 MHz.
Altera_Forum
Honored Contributor
16 years ago
Assuming the ADC clock is sourced from the FPGA, you should be able to use an internal reference clock as well. But if your present solution serves it's purpose, there's no need to change anything.

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Stratix III EP3SL340c3 Diffrential IO data rate

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