Stratix III EP3SL340c3 Diffrential IO data rate

As i mentioned above, to use ALTLVDS, either i needed to use an internal PLL or external clock source. The PCB i used to interface ADC with HSTC was only connected to IO pins and Quartus wont let me place a PLL to those IO pins. To use external clock source, i needed a 80 MHz frame clock with 16% duty cycle as it is required by ALTLVDS. (80 MHz instead of 40 because ALTLVDS does not support 12 bits and i needed to go for 6 bit serdes thus doubling the frame rate) this sort of clock was not available from my ADC and using a PLL was not an option open to me. i tried this as u suggested and as i UNDERSTOOD but couldnt get far as i had no idea how to synchronize internal clock with the bit stream coming from ADC with out using a PLL.

Also i can get my design to work upto 500Mbps which is the IO limit for my device( i think i read it in stratix III handbook). i am happy with 40 MHz ( 480 Mbps) as it does the job for me with the oscillator i have available on ADC, although my ADC can go upto 50 MHz.