Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Stratix III EP3SL340c3 Diffrential IO data rate

Hi I have been working on DE3 board with the above mentioned FPGA for some months now. I am trying to deserialize 8 LVDS channels from an ADC. each channel is 12 bits and ADC can work upto 50 Mega...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Your solution sounds somewhat complicated, you should be able to run the shift register at 240 MHz directly. If you are not able to operate the design faster than 480 MBPS, the issue is most likely related to timing and possibly signal quality of the LVDS input. Of course, the data must be transfered to the slow (frame) clock, but that's not very critical, I think.

I also suggested to use hardware SERDES (=ALTLVDS Megafunction) with FPGA internal reference clock and DPA. Did you try it?