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Altera_Forum
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16 years ago

Stratix III EP3SL340c3 Diffrential IO data rate

Hi I have been working on DE3 board with the above mentioned FPGA for some months now. I am trying to deserialize 8 LVDS channels from an ADC. each channel is 12 bits and ADC can work upto 50 Mega...
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Altera_Forum
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16 years ago

Assuming the ADC clock is sourced from the FPGA, you should be able to use an internal reference clock as well. But if your present solution serves it's purpose, there's no need to change anything.