Some problems about altera_pll on cyclone V device

did you check RREF_TL on your board?

from pin Connection Guide:

reference pins

RREF_TL Input - Reference resistor for transceiver and PLL

If any PLL, REFCLK pin, or transceiver channel is used, you must connect each RREF pin on that

side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND. Otherwise, you may

connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace

from this pin to the resistor needs to be routed so that it avoids any aggressor signals.

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did you check RREF_TL on your board?

from pin Connection Guide:

reference pins

RREF_TL Input - Reference resistor for transceiver and PLL

If any PLL, REFCLK pin, or transceiver channel is used, you must connect each RREF pin on that

side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND. Otherwise, you may

connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace

from this pin to the resistor needs to be routed so that it avoids any aggressor signals.

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Also, make sure that the PLL settings and pin mappings are correct. I hate to state the obvious, but it is possible that the wrong input pin is selected for the PLL input clock or the PLL is set for a different input clock frequency.

Thank you for your advice, derim。

I just confirmed the input pins and found it correctly connected to the dedicated CLK3_P pin , so as my teammates.

If I use the external clock directly, the clock is OK. But if only the altera_pll exists, the system fails.

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Thank you for your advice, derim。

I just confirmed the input pins and found it correctly connected to the dedicated CLK3_P pin , so as my teammates.

If I use the external clock directly, the clock is OK. But if only the altera_pll exists, the system fails.

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Additional obvious check: is the reset pin pulled low? The PLL expects an active-high reset, not active low. In addition, is the PLL set to auto-lock in the settings?

Thank you and finally found the RREF_TL pin is unconnected. I think it may be the real reason.

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did you check RREF_TL on your board?

from pin Connection Guide:

reference pins

RREF_TL Input - Reference resistor for transceiver and PLL

If any PLL, REFCLK pin, or transceiver channel is used, you must connect each RREF pin on that

side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND. Otherwise, you may

connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace

from this pin to the resistor needs to be routed so that it avoids any aggressor signals.

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I faced the same problem and the PLL was not locking. The RREF_TL was left floating. The issue was partially solved after fixing this floating pin.

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Thank you for your advice, Sherif. Does your PLL work now?

You mentioned that your issur has been partially solved. I wonder what issue has not been solved now.

Thank you for your advice, Sherif. Does your PLL work now?

You mentioned that your issur has been partially solved. I wonder what issue has not been solved now.

The PLL issue was solved and it was working as expected.

The chip was new to me and it is a custom board not an evaluation one. So I had a lot of things to test.

But anyway, everything is good for me now. That RREF_TL caused me some hard time.