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Altera_Forum
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9 years ago

Some problems about altera_pll on cyclone V device

Hello everyone, I just met a problem about altera_pll on my cyclone V board. There is a 5CEFA4F23C8 FPGA on my board and the FPGA is conneted to a crystal oscillator via a clock input pin. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Thank you for your advice, derim。

I just confirmed the input pins and found it correctly connected to the dedicated CLK3_P pin , so as my teammates.

If I use the external clock directly, the clock is OK. But if only the altera_pll exists, the system fails.

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Additional obvious check: is the reset pin pulled low? The PLL expects an active-high reset, not active low. In addition, is the PLL set to auto-lock in the settings?