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Honored ContributorSome problems about altera_pll on cyclone V device
Hello everyone, I just met a problem about altera_pll on my cyclone V board. There is a 5CEFA4F23C8 FPGA on my board and the FPGA is conneted to a crystal oscillator via a clock input pin. ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- did you check RREF_TL on your board? from pin Connection Guide: reference pins
RREF_TL Input - Reference resistor for transceiver and PLL If any PLL, REFCLK pin, or transceiver channel is used, you must connect each RREF pin on that side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND. Otherwise, you may connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals. --- Quote End --- Also, make sure that the PLL settings and pin mappings are correct. I hate to state the obvious, but it is possible that the wrong input pin is selected for the PLL input clock or the PLL is set for a different input clock frequency.
