Some glitches in the simualtion waveforms

As I said before, you need your simulation input stimulus to meet the setup and hold requirements of the input pins. I think that is what FvM was referring to.

And I still think what you are calling glitches are not actually glitches. People usually use the word "glitch" for a disturbance on a signal that is less than a clock cycle long. I suspect that when you zoom in on your simulation waveforms you will see that whatever is happening on the problem output is a pulse that lasts for at least one full clock cycle.

Because you are doing a timing simulation, you are seeing the effects of everything that changes in the place and route. When you change anything in the source code including changing whether you have one component or both of them present, there is some randomness to the resulting change in the exact timing. It might be only coincidence that it appears to work with one component but not with both components. If you have any timing violations reported by TimeQuest or the Classic Timing Analyzer (assuming you have proper timing constraints), it is not surprising to get unexpected results in timing simulation.

Based on what you recommended, I re-wrote the code with a regular edge sensitive design structure. However, the result is the same. Maybe there is something other than the structure causes the problem...

Still debugging it.....

If the output signals are assigned inside the edge sensitive process, in other words, the signals are connected to FlipFlop outputs in your design, glitches can only occur in two cases, I think:

1. An asynchronous input overriding the synchronous operation is in effect.

2. An input signal is violating setup or hold timing requirement. In this case, your stimulating waveform would be the reason. if a similar situation is also expected in real operation, the respective signals should be synchronized to the clock before entering the logic.

You're able to recognize the reason in your simulation. If it's not obvious from a the displayed signals, you can add internal signals as outputs to the simulation. As already said, timing violation are also reported during simulation and can be traced in detail.

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1. An asynchronous input overriding the synchronous operation is in effect.

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When I looked in the RTL Viewer at the attached state of the design (with the unneeded signal removed from the sensitivity lists), I didn't see any asynchronous control signal used by the output register, and the register was driving the output pin directly with no logic between the pin and the register. This is why I think there is no glitching, only a synchronous change in the register output at each clock edge. The simulation waveform timescale was zoomed out too far to say there was glitching.